It was designed for use in all fields of FPGA development and experiments.
Communication
Digital Communication DSP（FPGA）
Network
100M/1G Interface，switch VLAN
USB：
USB2.0 Engine Development
CPU：
RISC-V CPU 32bit Ecosystem Dvelopment and Educational Experiments
Artificial Intelligence
Voice collection, speech recognition Image acquisition and image recognition, deep learning
Features
| 10CL040 | 10CL080 | |
| Logic elements (LEs) (K) | 40 | 80 |
| Memory blocks(9K) | 126 | 305 |
| LMemory block(Kb) | 1134 | 2745 |
| 18×18 multipliers | 126 | 244 |
| Phase-locked loop(PLL) | 4 | 4 |
| Global clock networks | 20 | 20 |
System Features:
-
- Sram： IS61WV25616 (2 pieces ) 256K x 32bit
-
- Spi： serial flash (16M bytes)
-
- JTAG: two jtag programmable interfaces
- power Supply： 12V adapter source
System Connectivity
- 10/100/1000 Mbps Ethernet
- Hdmi: Hdmi out (1920×1080@60Hz)
- USB to Serial Interface：USB-UART bridge
Interaction and Sensory Devices
- 8 Switches
- 7 Buttons (up , down, left, right, ok, menu, return)
- 1 Reset button
- 8 LEDs
- 1 4-digit 7 segment display
- 1 I2c interface (24c02 eeprom)
- High resolution graphic LCD interface
- Image input interface
Expansion Connectors
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- 4 gpio connectors (compatible with digilent Pmod)
Features and Benefits
- gpio (16 ) 2×8 standard 2.54mm connectors (pin)
- led outport (8 个) 0603 smd
- switch (8 in one group) smd
- 7 Buttons (up , down, left, right, ok, menu, return)
- i2c 24c02 smd soic
- spi flash MX25L6433F 8-SOP (8M bytes)
- usb2uart ft2232C/H (2 uart ) Or cp2102 (1 uart)
- jtag 2×5 standard 2.54mm connectors(pin)
- eth 1G CAT5 Ethernet (rtl8111e)
- Digital tube 7seg (4) oasistek TOF-5421BMRL-N
- Hdmi out adv7511， hdmi_adv7511.SchDoc
- Test Port： 1×6 Standard 2.54mm connector （pin）
After nearly a decade of neglect, the last year has seen a big uptick in the adoption of the the RISC-V standard. The arrival of the first commercially-available open source system-on-chip (SoC) based on the architecture — the 32-bit Freedom Everywhere 310 — along with the first Arduino-compatible development board called the HiFive1, from the Bay Area startup SiFive, was seen as a real milestone by the open hardware community.
Which doesn’t mean that keeping other independent implementations of the standard around isn’t still important, which is where DarkRISCV comes in.
While the DarkRISCV implementation is not as full featured as some other RISC-V implementations, it does implement most of the RISC-V RV32I instruction set and works on real Spartan-6 hardware.
With the first GAP8 processor samples by Open-Silicon shipping, we’re almost in a place where we have multiple vendors producing open silicon built around the RISC-V core, and when that happens we’ll be in a very different place. At that point, we’re in a real open hardware environment because we no longer have vendor lock in, and it’s going to be interesting to see whether that makes a difference to the availability of boards based on RISC-V.
Until then, however, the availability of implementations of the RISC-V architecture, and the ability for people to get hands on with it—whether that’s using an FPGA or not—is important to the ecosystems continued health.
Full details of the DarkRISCV implementation, as well as some interesting notes with indications of not just what, and how, he implemented various parts of the standard, but also why Samsoniuk took certain paths are available in the project’s GitHub repo.