Menu Close

ARTIX 100T, XC7A100T, RISC-V FPGA Board

FII-PRX100 Educational Platform Educational Plaform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

FII-PRX100 Educational Platform Educational Plaform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

Features:

Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .3-stage pipelinearchitecturesupport machine mode onlyFrom instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood. The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA. Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)2 UART3 QSPII2C3 PWM10M/100M/1G ethernetWatchdog32 GPIO4 7-seg display interfaceExternal Serial FlashDebug Interfaces: JTAG12-Bit ADCFour data lines I2S and can support maximum of 8 audio outputs or 4 stereo channelsHardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

The entire system is designed by the verilog language, and all IPs can be added, deleted and reconfigured.